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[Other resource] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23722 | Author: Jawen | Hits:

[Windows Develop] fifo源程序

Description: fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
Platform: | Size: 1136 | Author: 许 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: first in first out VHDL code
Platform: | Size: 1024 | Author: LXG | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[Software Engineering] fifo_template

Description: aes code with fifo control to memory
Platform: | Size: 9216 | Author: allen | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
Platform: | Size: 10240 | Author: wei | Hits:

[VHDL-FPGA-Verilog] pgm

Description: uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
Platform: | Size: 205824 | Author: libin | Hits:

[VHDL-FPGA-Verilog] SLAVE_FIFO_16BITS

Description: 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
Platform: | Size: 1625088 | Author: xinsheng | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[VHDL-FPGA-Verilog] Flag-of-asynchronous-FIFO

Description: Quartus平台，VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
Platform: | Size: 82944 | Author: | Hits:

[Other] FIFO

Description: vhdl code for first in first out
Platform: | Size: 1024 | Author: amma | Hits:

[e-language] fifo

Description: This VHDL code for FIFO that is used in a NOC router-This is VHDL code for FIFO that is used in a NOC router
Platform: | Size: 1024 | Author: Anish Goel | Hits:

[Communication-Mobile] fifo

Description: fifo buffer in vhdl, first in first out in vhdl, vhdl code
Platform: | Size: 1024 | Author: sgma | Hits:

[e-language] aFifo

Description: Function : Asynchronous FIFO VHDL CODE
Platform: | Size: 2048 | Author: amin | Hits:

[VHDL-FPGA-Verilog] FPGA-FIFO-VHDL

Description: 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware description language, content analysis, with complete code
Platform: | Size: 74752 | Author: yanjiajun | Hits:

[VHDL-FPGA-Verilog] SLAVE-FIFO-8BITS

Description: EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
Platform: | Size: 1676288 | Author: Eddie | Hits:

[VHDL-FPGA-Verilog] fifo

Description: VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
Platform: | Size: 58368 | Author: gnc | Hits:

[Other] FIFO

Description: first input and first output vhdl code
Platform: | Size: 357376 | Author: mahdi | Hits:

[VHDL-FPGA-Verilog] CCD_Array

Description: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
Platform: | Size: 3320832 | Author: muralidh | Hits:

[VHDL-FPGA-Verilog] fifo-vhdl

Description: code fifo by spartan6
Platform: | Size: 14513 | Author: dornabit | Hits:
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